专业要求：

1. Analog and Mixed signal IC custom layout design.

2. Chip/Top level floorplanning and integration (Senior layout engineer).

职位描述：

1. Familiar with Cadence design environment (Virtuoso) and Verification such as Mentor Calibre.

2. Industry experience in layout of analog and mixed-signal ICs, such as high speed (GHz) analog circuits including PLLs and high-speed I/Os, etc.

3. Good understanding of design rules, device matching, and isolation techniques.

4. Basic understanding of semiconductor devices and IC process manufacturing.

5. Experience in top level floorplanning and integration is a plus.

6. BS degree in Electrical Engineering or Microelectronics.