Functions:
Analog and Mixed signal IC custom layout design.
Chip/Top level floorplanning and integration (Senior layout engineer).
Requirements:
Familiar with Cadence design environment (Virtuoso) and Verification such as Mentor Calibre.
More than 5-years Industry experience in layout of analog and mixed-signal ICs, such as high speed (GHz) analog circuits including PLLs and high-speed I/Os, etc.
Good understanding of design rules, device matching, and isolation techniques.
Basic understanding of semiconductor devices and IC process manufacturing.
Experience in top level floorplanning and integration is a plus.
BS degree in Electrical Engineering or Microelectronics.

职位福利：五险一金、年底双薪、绩效奖金、餐补、采暖补贴、带薪年假、补充医疗保险、员工旅游

职位亮点：发展前景好，诚聘热爱模拟版图设计的人才